In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
P E R I P H E R A L S
● Three 8 bit I/O ports
○ Three 8-bit corresponding TRIS registers
● Timer 0
● Single Design license for
○ 8-bit timer/counter
○ VHDL, Verilog source code called HDL Sour-
○ Readable and Writable
ce
○ 8-bit software programmable prescaler
○ Internal or external clock select
○ Edge select for external clock
● Watchdog Timer
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Configurable Time out period
○ 7-bit software programmable prescaler
○ Dedicated independent Watchdog Clock input
○ Netlist
● Upgrade from
D E L I V E R A B L E S
Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted Megafunction or/and
◊ plain text EDIF
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
♦
♦
♦
C O N F I G U R A T I O N
The following parameters of the DFPIC165X
core can be easy adjusted to requirements of
dedicated application and technology. Con-
figuration of the core can be prepared by ef-
fortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
Example application
Technical support
-
-
synchronous
asynchronous
RAM memory type
RAM size
•
•
•
•
•
•
•
•
♦
♦
♦
-
-
up to 256
default 128
◊ IP Core implementation support
◊ 3 months maintenance
-
-
up 4 kWords
default 2k
Program Memory size
●
Delivery the IP Core updates, minor
and major versions changes
Number of hardware stack
levels
-
-
1-8
default 2
●
●
Delivery the documentation updates
Phone & email support
-
-
used
unused
SLEEP mode
L I C E N S I N G
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
-
-
used / width
unused
WATCHDOG Timer
Timer system
-
-
used
unused
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
-
-
used
unused
PORTS A,B,C
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
