欢迎访问ic37.com |
会员登录 免费注册
发布采购

DFPIC165X 参数 Datasheet PDF下载

DFPIC165X图片预览
型号: DFPIC165X
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能的8位RISC微控制器 [High Performance 8-bit RISC Microcontroller]
分类和应用: 微控制器
文件页数/大小: 6 页 / 188 K
品牌: DCD [ DIGITAL CORE DESIGN ]
 浏览型号DFPIC165X的Datasheet PDF文件第1页浏览型号DFPIC165X的Datasheet PDF文件第2页浏览型号DFPIC165X的Datasheet PDF文件第3页浏览型号DFPIC165X的Datasheet PDF文件第5页浏览型号DFPIC165X的Datasheet PDF文件第6页  
Indirect addressing is possible by using the  
INDF register. Any instruction using INDF reg-  
ister actually accesses data pointed to by the  
file select register FSR. Reading INDF register  
indirectly will produce 00h. Writing to the INDF  
register indirectly results in a no-operation. An  
effective 8-bit address is obtained from an 8-  
bit FSR register.  
O P T I O N A L  
P E R I P H E R A L S  
There are also available an optional pe-  
ripherals,  
not  
included  
in  
presented  
DFPIC165X Microcontroller Core. The op-  
tional peripherals, can be implemented in mi-  
crocontroller core upon customer request.  
Timer 0 – Main system’s timer and prescaler.  
The DFPIC165X Timer operates in two  
modes: 8-bit timer or 8-bit counter. In the  
“timer mode”, timer registers are incremented  
every 4 CLK periods. When the prescaler is  
assigned into the TIMER prescale ration can  
be divided by 2, 4 .. 256. In the “counter  
mode” the timer register is incremented every  
falling or rising edge of T0CKI pin, dependent  
on T0SE bit in OPTION register.  
Full duplex UART  
SPI – Master and Slave Serial Peripheral  
Interface  
Supports speeds up ¼ of system clock  
Mode fault error  
Write collision error  
Software selectable polarity and phase of se-  
rial clock SCK  
System errors detection  
Watchdog Timer – it is a free running timer.  
WDT has own clock input separate from sys-  
tem clock. It means that the WDT will run  
even if the system clock is stopped by execu-  
tion of SLEEP instruction. During normal op-  
eration, a WDT timeout generates a Watch-  
dog reset. If the device is in SLEEP mode the  
WDT timeout causes the device to wake-up  
and continue with normal operation.  
Allows operation from a wide range of system  
clock frequencies (build-in 5-bit timer)  
Interrupt generation  
PWM – Pulse Width Modulation Timer  
2 independent 8-bit PWM channels, concate-  
nated on one 16-bit PWM channel  
Software-selectable duty from 0% to 100% and  
pulse period  
I/O Ports – Block contains DFPIC165X’s gen-  
eral purpose I/O ports and data direction reg-  
isters (TRIS). The DFPIC165X has three 8-bit  
full bi-directional ports PORT A, PORT B and  
PORT C. Read and write accesses to the I/O  
port are performed via their corresponding  
SFR’s PORTA, PORTB, PORTC. The reading  
instruction always reads the status of Port  
pins. Writing instructions always write into the  
Port latches. Each port’s pin has an corre-  
sponding bit in TRISA, TRISB and TRISC reg-  
isters. When the bit of TRIS register is set this  
means that the corresponding bit of port is  
configured as an input (output drivers are set  
into the High Impedance).  
Software-selectable polarity of output wave-  
form  
I2C bus controller - Master  
7-bit and 10-bit addressing modes  
NORMAL, FAST, HIGH speeds  
Multi-master systems supported  
Clock arbitration and synchronization  
User defined timings on I2C lines  
Wide range of system clock frequencies  
Interrupt generation  
I2C bus controller - Slave  
NORMAL speed 100 kbs  
FAST speed 400 kbs  
HIGH speed 3400 kbs  
Wide range of system clock frequencies  
User defined data setup time on I2C lines  
Interrupt generation  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.