B L O C K D I A G R A M
P I N S D E S C R I P T I O N
PIN
TYPE
DESCRIPTION
clk
input Global clock
clk
por
Hardware
Stack
clkwdt
input Watchdog clock
ALU
por
input Global reset Power On Reset
input User reset
mclr
ramdatai
ramdatao
ramaddr
ramwe
ramoe
prgdata[11:0]
ramdati[7:0]
t0cki
input Data bus from program memory
input Data bus from int. data memory
input Timer 0 input
mclr
sleep
prgdata
prgaddr
Control
Unit
RAM
Controller
portai[7:0]
portbi[7:0]
portci[7:0]
prgdata[11:0]
ramdati[7:0]
prgaddr[11:0]
ramdatao[7:0]
ramaddr[7:0]
ramwe
input Port A input
input Port B input
portai
portbi
portci
portao
portbo
portco
trisa
Timer 0
t0cki
input Port C input
input Data bus from program memory
input Data bus from int. data memory
output Program memory address bus
output Data bus for internal data memory
output RAM address bus
I/O
Ports
Watchdog
Timer
clkwdt
trisb
trisc
output Data memory write
output Data memory output enable
output Sleep signal
ramoe
ALU – Arithmetic Logic Unit performs arithme-
tic and logic operations during execution of an
instruction. This module contains work register
(W) and Status register.
sleep
portao[7:0]
portbo[7:0]
portco[7:0]
trisa[7:0]
trisb[7:0]
trisc[7:0]
output Port A output
output Port B output
Control Unit – It performs the core synchroni-
zation and data flow control. This module
manages execution of all instructions. Per-
forms decode and control functions for all
other blocks. It contains program counter (PC)
and hardware stack.
output Port C output
output Data direction pins for Port A
output Data direction pins for Port B
output Data direction pins for Port C
Hardware Stack – The DFPIC165X configur-
able hardware stack. The stack space is not a
part of either program or data space and the
stack pointer is not readable or writable. The
PC is pushed onto the stack when CALL in-
struction is executed or an interrupt causes a
branch. The stack is popped while RETLW
instruction execution. The stack operates as a
circular buffer. This means that after the stack
has been pushed two times, the third push
overwrites the value that was stored from the
first push.
S Y M B O L
clk
clkwdt
por
mclr
prgdata(11:0)
ramdatai(7:0)
prgaddr(11:0)
ramdatao(7:0)
ramaddr(7:0)
ramwe
ramoe
t0cki
sleep
RAM Controller – It performs interface func-
tions between Data Memory and DFPIC165X
internal logic. It assures correct Data memory
portai(7:0)
portbi(7:0)
portci(7:0)
portao(7:0)
portbo(7:0)
portco(7:0)
addressing
and
data
transfers.
The
DFPIC165X supports two addressing modes:
direct or indirect. In Direct Addressing the 8-bit
direct address is computed from FSR(7:5) bits
5 least significant bits of instruction word.
trisa(7:0)
trisb(7:0)
trisc(7:0)
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