Interrupt Controller - D16750 consists fully
prioritized interrupt system controller. It
entering the Rx shift register will set the
Overrun Error flag.
controls interrupt requests to the CPU and
interrupt priority. Interrupt controller contains
Transmitter
Control
module
controls
transmission of written to THR (Transmitter
Holding register) character via serial output
SO. The new transmission starts on the next
overflow signal of internal baud generator,
after writing to THR register or Transmitter
FIFO. Transmission control contains THR
register and transmitter shift register.
Interrupt
Enable
(IER)
and
Interrupt
Identification (IIR) registers.
Receiver
Control
addr(2:0)
datai(7:0)
datao(7:0)
rclk
rclken
si
&
Shift Register
rd
wr
cs
Data Bus
Buffer
Transmitter FIFO - the Tx portion of the
UART transmits data through SO as soon as
the CPU loads a byte into the Tx FIFO. The
UART will prevent loads to the Tx FIFO if it
currently holds 64 (128, 256, 512) characters
(depending on FCR(5) bit value and selected
FIFO size). Loading to the Tx FIFO will again
be enabled as soon as the next character is
transferred to the Tx shift register. These
ddis
txrdy
rxrdy
RCVR Buffer
&
RCVR FIFO
rts
cts
dtr
dsr
dcd
ri
Transmitter
Control
so
Modem
control
logic
&
Shift Register
capabilities
account
for
the
largely
autonomous operation of the Tx. The UART
starts the above operations typically with a Tx
interrupt.
out1
out2
THR Buffer
&
THR FIFO
P E R F O R M A N C E
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
baudclk
baudclken
baudout
Baud
Generator
Interrupt
Controller
intr
clk
rst
Speed
grade
-6
Device
Logic Cells
Fmax
CYCLONE
CYCLONE2
STRATIX
STRATIX2
STRATIXGX
MERCURY
EXCALIBUR
APEX II
APEX20KC
APEX20KE
APEX20K
ACEX1K
4841
4991
4841
4181
4841
5401
5111
5121
5111
5111
5111
5431
5431
149 MHz
160 MHz
158 MHz
255 MHz
163 MHz
136 MHz
112 MHz
145 MHz
135 MHz
96 MHz
Receiver Control - Receiving starts when the
falling edge on Serial Input (SI) during IDLE
State is detected. After starting the SI input is
sampled every 16 internal baud cycles as it is
shown in figure below. When the logic 1 state
is detected during START bit it means that the
False Start bit was detected and receiver back
to the IDLE state.
-6
-5
-3
-5
-5
-1
-7
-7
-1
-1
-1
-1
Receiver FIFO - The Rx FIFO can be 64
(128, 256, 512) levels deep, it receives data
until the number of bytes in the FIFO equals
the selected interrupt trigger level. At that time
if Rx interrupts are enabled, the UART will
issue an interrupt to the CPU. The Rx FIFO
will continue to store bytes until it is full, and
will not accept any next byte. Any more data
87 MHz
93 MHz
94 MHz
FLEX10KE
1- FIFOs implemented in EAB’s – 1216 Bits
Core performance in ALTERA® devices
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
