● Two DMA Modes allows single and multi-
K E Y F E A T U R E S
● Software compatible with 16450, 16550
transfer
● Technology independent HDL Source
and 16750 UARTs
Code
● Configuration capability
● Full prioritized interrupt system controls
● Separate configurable BAUD clock line
● Fully synthesizable static design with no
● Two modes of operation: UART mode and
internal tri-state buffers
FIFO mode
A P P L I C A T I O N S
● Majority Voting Logic
● Serial Data communications applications
● In the FIFO mode transmitter and receiver
are each buffered with 16 byte or 64 byte
FIFO to reduce the number of interrupts
presented to the CPU
● Modem interface
L I C E N S I N G
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
● Optional FIFO size extension to 128, 256
or 512 Bytes
● Adds or deletes standard asynchronous
communication bits (start, stop, and parity)
to or from the serial data
Single Design license allows use IP Core in
single
FPGA
bitstream
and
ASIC
implementation.
● In UART mode receiver and transmitter
are double buffered to eliminate a need for
precise synchronization between the CPU
and serial data
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time
restriction except One Year license where
time of use is limited to 12 months.
● Independently controlled transmit, receive,
line status, and data set interrupts
● False start bit detection
● 16 bit programmable baud generator
● Single Design license for
● MODEM control functions (CTS, RTS,
DSR, DTR, RI, and DCD)
○
VHDL, Verilog source code called HDL
Source
● Programmable automatic Hardware Flow
Control logic through Auto-RTS and Auto-
CTS
○
Encrypted, or plain text EDIF called Netlist
● One Year license for
Encrypted Netlist only
● Unlimited Designs license for
● Fully
programmable
serial-interface
○
characteristics:
○
○
5-, 6-, 7-, or 8-bit characters
○
○
HDL Source
Netlist
Even, odd, or no-parity bit generation and
detection
○
○
1-, 1½-, or 2-stop bit generation
Baud generation
● Upgrade from
○
○
HDL Source to Netlist
Single Design to Unlimited Designs
● Complete status reporting capabilities
● Line break generation and detection.
Internal diagnostic capabilities:
○
○
Loop-back controls for communications link
fault isolation
Break, parity, overrun, framing error
simulation
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
