D E L I V E R A B L E S
D E S I G N F E A T U R E S
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♦
Source code:
The functionality of the D16750 core was
based on the Texas Instruments TL16C750A.
The following characteristics differentiate the
D16750 from Texas Instruments devices:
● The bi-directional data bus has been split
into two separate buses: datai(7:0),
datao(7:0)
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench
environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
● Signals rd2 and wr2, xin, and xout have
been removed from interface
♦
● Signal ADS and address latch have been
removed
◊ HDL core specification
◊ Datasheet
Synthesis scripts
● The DLL, DLM and THR registers are
♦
♦
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reset to all zeros
Example application
● TEMT and THRE bits of Line Status
Register, are reset during the second
clock rising edge following a THR write
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
● RCLK clock is replaced by global clock
CLK, internally divided by BAUD factor.
●
●
● Asynchronous microcontroller interface is
replaced by equivalent Universal interface
● All latches implemented in original 16750
devices are replaced by equivalent flip-flop
registers, with the same functionality
C O N F I G U R A T I O N
The following parameters of the D16750 core
can be easy adjusted to requirements of
dedicated
application
and
technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
- enable
- disable
Baud generator
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•
•
•
•
•
•
- enable
- disable
External RCLK source
External BAUDCLK source
Modem Control logic
SCR Register
- enable
- disable
- enable
- disable
- enable
- disable
- enable
- disable
FIFO Control logic
FIFO size
- standard 16/64
- large up to 512
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
