A P P L I C A T I O N
S Y M B O L
rst
clk
addr
addr(2:0)
clk
rst
baudclk
rclk
addr
latch
baudout
rclk
baudclk
CPU
ale
intr
D16750
datai(7:0)
address(2:0)
datao(7:0)
datao(7:0)
datai(7:0)
datai(7:0)
datao(7:0)
wr
rd
cs
intr
so
si
wr
rd
cs
ddis
txrdy
rxrdy
we
rd
cs
int
rts
dtr
dsr
dcd
cts
ri
D16750
EIA
Drivers
so
si
cts
dsr
dcd
ri
rts
dtr
out1
out2
rxrdy
txrdy
out1
out2
baudclken
rclken
baudclken
rclken
Typical D16750 and processor connection is
shown in figure above.
P I N S D E S C R I P T I O N
B L O C K D I A G R A M
PIN
TYPE
DESCRIPTION
Data Bus Buffer - The data Bus Buffer
accepts inputs from the system bus and
generates control signals for the other D16750
functional blocks. Address bus ADDR(2:0)
selects one of the register to be read
from/written into. Both RD and WE signals are
active low, and are qualified by CS; RD and
WE are ignored unless the D16750 has been
selected by holding CS low.
rst
input Global reset
clk
input Global clock
datai[7:0]
addr[2:0]
cs
input Parallel data input
input Address bus
input Chip select input
input Write input
wr
rd
input Read input
rclk
input Receiver clock
baudclk
si
input Baud generator clock
input Serial data input
input Clear to send input
input Data set ready input
input Data carrier detect input
input Ring indicator input
input Baud generator clock enable
input Receiver clock enable
output Baud generator output
output Parallel data output
output Serial data output
output Driver disable output
output Transmitter ready output
output Receiver ready output
output Request to send output
output Data terminal ready output
output Output 1
Baud Generator - The D16750 contains a
programmable 16 bit baud generator that
divides clock input by a divisor in the range
between 1 and (216–1). The output frequency
of the baud generator is 16× the baud rate.
The formula for the divisor is:
cts
dsr
dcd
ri
frequency
baudclken
rclken
baudout
datao[7:0]
so
divisor =
baudrate *16
Two 8-bit registers, called divisor latches DLL
and DLM, store the divisor in a 16-bit binary
format. These divisor latches must be loaded
during initialization of the D16750 in order to
ensure desired operation of the baud
generator. When either of the divisor latches
is loaded, a 16-bit baud counter is also loaded
on the CLK rising edge following the write to
DLL or DLM to prevent long counts on initial
load.
ddis
txrdy
rxrdy
rts
dtr
out1
out2
intr
output Output 2
output Interrupt request output
Modem Control Logic controls the interface
with the MODEM or data set (or a peripheral
device emulating a MODEM).
Note: When enabled RCLK and BAUDCLK pins
frequency should be at least two times lower
than CLK, 2*fRCLK< fCLK
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are trademarks of their respective owners.
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
