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SLLS763B – JANUARY 2007 – REVISED MARCH 2007
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
CLOCK PINS
REFCLKP,
REFCLKN
RXCLKP,
RXCLKN
TXCLKP,
TXCLKN
TXCLKSRCP,
TXCLKSRCN
SERIAL SIDE DATA PINS
SRXDIP,
SRXDIN
STXDOP,
STXDON
14
15
9
8
PECL compatible
input
PECL compatible
input
Receive differential pairs; high-speed serial inputs.
Transmit differential pairs; high-speed serial outputs.
94
95
67
68
79
80
70
71
LVDS/PECL
compatible input
LVDS output
LVDS input
LVDS output
Differential reference input clock. There is an on-chip 100-Ω termination resistor differentially
placed between REFCLKP and REFCLKN. The dc bias is also provided on-chip for ac-coupled
case.
Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The interface of
RXDATA(0:3) and RXCLKP is source synchronous (see
Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of TXCLKP.
Transmit clock source. A clock source generated from the SLK2511B to the downstream device
(i.e., framer) that could be used by the downstream device to transmit data back to the SLK2511B.
This clock is frequency-locked to the local reference clock.
NO.
TYPE
DESCRIPTION
PARALLEL SIDE DATA PINS
FSYNCP,
FSYNCN
RXDATA[0:3]
P/N
RXPARP,
RXPARN
TXDATA[0:3]
P/N
TXPARP,
TXPARN
CONTROL/STATUS PINS
AUTO_DETECT
34
TTL input (with
pulldown)
TTL input (with
pulldown)
TTL input (with
pullup)
TTL input (with
pullup)
TTL input (with
pullup)
TTL input (with
pulldown)
TTL output
Data rate autodetect enable. Enable the auto-detection function for different data rates. When
AUTO_DETECT is high, the autodetection circuit generates RATEOUT0 and RATEOUT1 to
indicate the data rates for the downstream device.
Configuration pins. Put the device under one of the four operation modes: TX only, RX only,
transceiver, or repeater mode. (See
Standby enable. When this pin is held low, the device is disabled for IDDQ testing. When high, the
device operates normally.
Frame sync enable. When this pin is asserted high, the frame synchronization circuit for byte
alignment is turned on.
Lock to reference. When low, RXCLKP/N output is forced to lock to REFCLK. When high,
RXCLKP/N is the divided down clock extracted from the receive serial data.
Local loopback enable. When high, the serial output is internally looped back to its serial input.
Loss of lock. When the clock recovery loop has locked to the input data stream and the phase
differs by less than 100 ppm from REFCLK then LOL is high. When the phase of the input data
stream differs by more than 100 ppm from REFCLK, then LOL is low. If the difference is too big (>
500 ppm), the LOL output is not valid.
Loop timing mode. When high, the PLL for clock synthesizer is bypassed. The recovered clock
timing is used to send the transmit data.
Loss of signal. When no transitions appear on the input data stream for more than 2.3
µs,
a loss of
signal occurs and LOS goes high. The device also transmits all zeroes downstream using REFCLK
as its clock source. When a valid SONET signal received the LOS signal goes low.
PRBS testing enable. When this pin is asserted high, the device is put into the PRBS testing mode.
Programmable de-emphasis control. Combinations of these two bits can be used to optimize serial
data transmission.
Polarity select. This pin, used with the SIGDET pin, sets the polarity of SIGDET. When high,
SIGDET is an active low signal. When low, SIGDET is an active high signal.
Autorate detection outputs. When AUTO_DETECT is high, the autodetection circuit generates
these two bits to indicate the data rates for the downstream device.
TXFIFO and LOL reset pin. Low is reset and high is normal operation.
73
74
66–63,
60–57
56
55
88–81
99
98
LVDS output
Frame sync pulse. This signal indicates the frame boundaries of the incoming data stream. If the
frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and RXCLKN clock cycles when it
detects the framing patterns.
Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP (seeFigure
).
RXDATA0 is the first bit received in time.
Receive data parity output
Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP. TXDATA0 is
the first bit transmitted in time.
Transmit data parity input
LVDS output
LVDS output
LVDS input
LVDS input
CONFIG0,
CONFIG1
ENABLE
FRAME_EN
LCKREFN
LLOOP
LOL
17
18
44
27
24
53
45
LOOPTIME
LOS
51
46
TTL input (with
pulldown)
TTL output
PRBSEN
PRE1, PRE2
PS
RATEOUT0,
RATEOUT1
RESET
41
4 and 5
21
37
36
48
TTL input (with
pulldown)
TTL input (with
pulldown)
TTL input (with
pulldown)
TTL output
TTL input
4
DBLECTRO [ DB LECTRO INC ]
