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SLK2511BPZP 参数 Datasheet PDF下载

SLK2511BPZP图片预览
型号: SLK2511BPZP
PDF下载: 下载PDF文件 查看货源
内容描述: OC- 48/24 /12/3 SONET / SDH的多速率收发 [OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER]
分类和应用: 电信集成电路异步传输模式ATM
文件页数/大小: 21 页 / 573 K
品牌: DBLECTRO [ DB LECTRO INC ]
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www.ti.com
SLLS763B – JANUARY 2007 – REVISED MARCH 2007
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
V
DD
Supply voltage
TTL input terminals
Voltage range
P
D
T
stg
T
A
LVDS terminals
Any other terminal except aboven
Package power dissipation
Storage temperature
Electrostatic discharge
Characterized free-air operating temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
–0.3 to 3
–0.3 to 4
–0.3 to 3
–0.3 to V
DD
+ 0.3
See Dissipation Rating Table
–65 to 150
HBM: 2 kv
–40 to 85
260
°C
°C
°C
UNIT
V
V
V
V
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
PZP
(2)
PZP
(3)
(1)
(2)
(3)
T
A
25°C
POWER RATING
3.4 W
2.27 W
DERATING FACTOR
(1)
ABOVE T
A
= 25°C
33.78 mW/°C
22.78 mW/°C
T
A
= 85°C
POWER RATING
1.3 W
0.911 W
This is the inverse of the traditional junction-to-ambient thermal resistance (R
θJA
).
2 oz trace and copper pad with solder.
2 oz trace and copper pad without solder.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
V
DD
P
D
T
A
Supply voltage
Power dissipation
Shutdown current
Frequency = 2.488 Gb/sec, PRBS pattern
Enable = 0, VDDA, VDD pins, VDD = max
– 40
2.375
NOM
2.5
900
20
85
MAX
2.625
1100
UNIT
V
mW
µA
°C
Operating free-air temperature
START-UP SEQUENCE
To ensure proper start up, follow one of the following steps when powering up the SLK2511B.
1. Keep ENABLE (pin 44) low until power supplies and reference clock have become stable.
2. Drive ENABLE (pin 44) low for at least 30 ns after power supplies and reference clock have become
stable.
The following step is recommended with either of the above two sequences.
3. Drive RESET low for at least 10 ns after link has become stable to center the TXFIFO.
12