SLK2511B
www.ti.com
SLLS763B–JANUARY 2007–REVISED MARCH 2007
TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
REFERENCE CLOCK (REFCLK)
Frequency tolerance(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–20
20
ppm
Duty cycle
40%
50%
60%
3
Jitter
12 kHz to 20 MHz
ps rms
PLL PERFORMANCE SPECIFICATIONS
PLL startup lock time
VDD, VDDC = 2.3 V, after REFCLK is stable
Valid SONET signal or PRBS OC-48
1
ms
Acquisition lock time
2031
850
Bit Times
SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS
PRE1 = 0, PRE2 = 0, Rt = 50,
See Table 5 and Figure 1
650
1000
V(ODD) = |STXDOP-STXDON|, transmit
differential output voltage under
de-emphasis
PRE1 = 1, PRE2 = 0
PRE1 = 0, PRE2 = 1
PRE1 = 1, PRE2 = 1
Rt = 50Ω
550
540
750
700
900
860
mV
500
650
800
V(CMT)
Transmit common mode voltage range
1100
150
1250
1400
mV
mV
Receiver Input voltage requirement,
VID=|SRXDIP–SRXDIN|
V(CMR)
Receiver common mode voltage range
Receiver input leakage
1100
-550
80
1250
100
2250
550
120
1
mV
µ A
Ω
Il
Rl
Receiver differential impedance
Receiver input capacitance
CI
pF
td(TX_Latency)
td(RX_Latency)
50
Bit Times
50
(1) The ±20 ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH compliant systems, looser tolerances may
apply.
SERIAL DIFFERENTIAL SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Differential signal rise time (20% to 80%)
Output jitter
TEST CONDITIONS
MIN
TYP
100
MAX
140
0.1
UNIT
ps
tt
tj
RL = 50Ω
80
Jitter-free data, 12 kHz to 20 MHz, RLOOP = 1
RLOOP = 1, See Figure 2
0.05
UI(pp)
Jitter tolerance
Jitter transfer
RLOOP = 1, See Figure 2
14
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