SLK2511B
www.ti.com
SLLS763B–JANUARY 2007–REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
TTL
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
Input high current
2
3.6
0.80
40
V
V
VDD = MAX, VIN = 2 V
VDD = MAX, VIN =0.4 V
IOH = –1 mA
µA
µA
V
IIL
Input low current
–40
VOH
VOL
CI
High-level output voltage
Low-level output voltage
Input capacitance
2.10
2.3
IOH = 1 mA
0.25
0.5
4
V
pF
LVDS INPUT SIGNALS
VI
Input voltage
825
250
200
1575
mV
mV
Assumes 60% / 40% duty cycle
Assumes 55% / 45% duty cycle
20% to 80%
Input differential threshold voltage
See Figure 5
VID(th)
tr/tf
CI
Input transition time
375
3
ps
pF
Ω
Input capacitance
RI
Input differential impedance
Input setup time requirement
Input hold time requirement
Input clock duty cycle
On-chip termination
See Figure 8
80
300
300
40%
100
120
tsu
ps
ps
th
See Figure 8
T(duty)
60%
LVDS OUTPUT SIGNALS
VOD
VOS
VOD
VOS
Output differential voltage
300
800
1375
25
Output common mode voltage
Change VOD between 1 and 0
Change VOS between 1 and 0
1070
RL = 100 ±1%
mV
25
I(SP), I(SN)
I(SPN)
,
Output short circuit current
Power-off current
Outputs shorted to ground or shorted together
VDD = 0 V
24
mA
Ioff
10
100
100
300
55%
7
µA
t(cq_min)
t(cq_max)
tr/tf
Clock-output time
See Figure 7
20% to 80%
ps
ps
Output transition time
100
45%
4
Output clock duty cycle
Data output to FRAME_SYNC delay
Bit times
(OC-48 = 622.08 MHz, Clock Rates With tr/tf ≤ 500 ps)
250
200
150
100
50
0
40 42 44 46 48 50 52 54 56 58 60
Input Duty-Cycle - %
Figure 5. LVDS Differential Input Voltage vs Input Duty Cycle
13
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