DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
6.24 TX/RX Memory Size Control Register (3FH)
Bit
Name
Default
Description
7:6
Reserved
PS0,RO
Reserved
TX Block Size in 2-Port Mode
This value defines the transmit block size in 256-byte unit.
TX memory size = TX_SIZE * 256 bytes
And then
5:0
TX_SIZE
P20h,RW
RX memory size = 16KB – (TX_SIZE + 1)*256-Byte
Note: The value of TX_SIZE should be between 14H and 30H
6.25 Switch Control Register (52H)
Bit Name Default
MEM_BIST PH0,RO
Description
Address Memory Test BIST Status
0: OK
7
1: Fail
6
5
RST_SW
RST_ANLG P0,RW
P0,RW
Reset Switch Core and auto clear after 10us
Reset Analog PHY Core and auto clear after 10us
4:3
SNF_PORT PE00,RW Sniffer Port Number
Define the port number to act as the sniffer port
CRC Checking Disable
2
CRC_DIS
AGE
PE0,RW
PE0,RW
When set, the received CRC error packet also accepts to receive memory.
Aging
1:0
00: no aging
01: 64 ± 32 sec
10: 128 ± 64 sec
11: 256 ±128 sec
6.26 VLAN Control Register (53H)
Bit
7
Name
TOS6
Default
PE0,RW Full ToS Using Enable
1: check most significant 6-bit of TOS
Description
0: check most significant 3-bit only of TOS
Reserved
PE0,RW Unicast packet can across VLAN boundary
PE0,RW Replace VIDFF
6
5
4
RESERVED
UNICAST
VIDFF
0,RO
If the received packet is a tagged VLAN with VID equal to “FFF”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace VID01
If the received packet is a tagged VLAN with VID equal to “001”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace VID0
3
2
VID1
VID0
If the received packet is a tagged VLAN with VID equal to “000”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace priority field in the tag with value define in Reg 6FH bit 7~5.
PE0,RW VLAN mode enable
1
0
PRI
VLAN
1: 802.1Q base VLAN mode enable
0: port-base VLAN only
22
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
