DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
6.27 DSP PHY Control Register (58H~59H)
58H:
Bit
7:0
Name
DSP_CTL1
Default
0,RW
Description
DSP Control Register 1 for testing only (register 58H)
59H:
Bit
7:0
Name
DSP_CTL2
Default
0,RW
Description
DSP Control Register 2 for testing only (register 59H)
6.28 Per Port Control/Status Index Register (60H)
Bit
7:5
4:2
1:0
Name
reserved
reserved
INDEX
Default
PHS0,RW reserved
Description
0,RO
reserved
PHS0,RW Port index for register 61H~84H
Write the port number to this register before write/read register 61H~84H.
Note: The processor port INDEX number is 3
6.29 Per Port Control Data Register (61H)
Bit
7
6
Name
RESERVED
PARTI_EN
Default
Description
PE0,RW Reserved
PE0,RW Enable Partition Detection
5
NO_DIS_RX PE0,RW Not Discard RX Packets when Ingress Bandwidth Control
When received packets bandwidth reach Ingress bandwidth threshold,
the packets over the threshold are not discarded but with flow control.
4
FLOW_DIS
PE0,RW Flow control in full duplex mode, or back pressure in half duplex mode
enable
0: enable
1: disable
3
2
1
0
BANDWIDTH PE0,RW Bandwidth Control
0: Control with Ingress and Egress separately, ref to Register 66H.
1: Control with Ingress or Egress, ref to Register 67H
PE0,RW Broadcast packet filter
BP_DIS
0: accept broadcast packets
1: reject broadcast packets
MP_DIS
PE0,RW Multicast packet filter
0: accept multicast packets
1: reject multicast packets
MP_STORM PE0,RW Broadcast Storm Control
0: only broadcast packets storm are controlled
1: multicast packets also same as broadcast storm control.
Preliminarydatasheet
DM9302-15-DS-P01
July 30, 2009
23
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
