DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
6.3 TX Control Register (02H)
Bit
7:4
3
2
1
Name
RESERVED
CRC_DIS2 PHS0,RW
RESERVED 0,RO
CRC_DIS1 PHS0,RW
TXREQ
Default
0,RO
Description
Reserved
CRC Appends Disable for Packet Index 2
Reserved
CRC Appends Disable for Packet Index 1
0
PHS0,RW TX Request. Auto clears after transmit completely
6.4 RX Control Register (05H)
Bit
7
6
Name
Default
Description
HASHALL PHS0,RW Filter All address in Hash Table
RESERVED PHS0,RW Reserved
5:4
3
RESERVED PHS0,RW Reserved
ALL
PHS0,RW Pass All Multicast Packets
All received packets with bit 0 is “1” of Destination Address (DA) field are accepted
and save to receive memory.
2
1
RESERVED PHS0,RW Reserved
PRMSC
PHS0,RW Promiscuous Mode
All received packets are accepted and save to receive memory without DA field filter.
0
RXEN
PHS0,RW RX Enable
6.5 RX Status Register (06H)
Bit
7:4
3:2
1
Name
RESERVED
SRCP
Default
0,RO
0,RO
Description
Reserved
Source Port Number
CE
PH0,RO CRC Error
It is set to indicate that the received frame ends with a CRC error
Reserved
0
RESERVED
0,RO
6.6 Receive Overflow Counter Register (07H)
Bit
7
Name
RXFU
Default
PHS0,R/C Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
PHS0,R/C Receive Overflow Counter
Description
6:0
ROC
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.7 Flow Control Register (0AH)
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
RX Flow Control Enable
Enables the pause packet for high/low water threshold control
Reserved
5
FLOW_EN PHS0,RW
RESERVED 0,RO
4:0
6.8 EEPROM & PHY Control Register (0BH)
Bit
7:6
5
Name
RESERVED
REEP
Default
0,RO
Description
Reserved
PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
PH0,RW Write EEPROM Enable
4
WEP
18
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
