DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
7:0
7:0
7:0
7:0
7:0
MAB4
MAB3
MAB2
MAB1
MAB0
X,RW
X,RW
X,RW
X,RW
X,RW
Multicast Address Byte 4 (1AH)
Multicast Address Byte 3 (19H)
Multicast Address Byte 2 (18H)
Multicast Address Byte 1 (17H)
Multicast Address Byte 0 (16H)
6.14 RX Packet Length Low Register ( 20H )
Bit
7:0
Name
RXPLL
Default
PH,RO
Description
Description
Description
RX Packet Length Low byte
6.15 RX Packet Length High Register ( 21H )
Bit
7:0
Name
RXPLH
Default
PH,RO
RX Packet Length High byte
6.16 RX Additional Status Register ( 26H )
Bit
7:4
1:0
Name
RESERVED
Default
0,RO
Reserved
uP received pointer status, only available when RX pointer restriction is enabled
(Reg27h.7=0).
RPTRS
PH,RO
00: Within buffer
01: End of buffer
1x: Exceed buffer
6.17 RX Additional Control Register ( 27H )
Bit
7
6:0
Name
RPRD
RESERVED
Default
Description
Description
Description
Description
PHS0,RW RX pointer restriction disable
0,RO
Reserved
6.18 Vendor ID Registers (28H~29H)
Bit
7:0
7:0
Name
VIDH
VIDL
Default
PE,0AH,RO
PE,46H.RO
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
6.19 Chip Revision Register (2CH)
Bit
7:0
Name
CHIPR
Default
01H,RO
CHIP Revision
6.20 Transmit Check Sum Control Register (31H)
Bit
7~3
2
1
0
Name
RESERVED
UDPCSE
TCPCSE
IPCSE
Default
0,RO
HP0,RW
HP0,RW
HP0,RW
Reserved
UDP Checksum Generation Enable
TCP Checksum Generation Enable
IP Checksum Generation Enable
20
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
