DM9016
3-port switch with Processor Interface
8.1 Basic Mode Control Register (BMCR) – 00H
Bit
Bit Name
Default
Description
15
Reset
0, RW/SC Reset
0=Normal operation
1=Software reset
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep returning a
value of one until the reset process is completed
Loopback
Loop-back control register
0 = Normal operation
14
13
Loopback
0, RW
1, RW
1 = Loop-back enabled
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
Speed Select
Speed selection
0 = 10Mbps
1 = 100Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
Auto-negotiation Enable
0= Auto-negotiation is disabled
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
12
11
Auto-negotiation
enable
1, RW
0, RW
Power down
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down
state and while in the power-down state, the PHY should not
generate spurious signals on the MII
0=Normal operation
1=Power down
10
9
Isolate
0,RW
Isolate
Force to 0 in application.
Restart
Auto-negotiation
0,RW/SC Restart Auto-negotiation
0 = Normal operation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until
auto-negotiation is initiated by the DM9016. The operation of the
auto-negotiation process will not be affected by the management
entity that clears this bit
8
Duplex mode
1,RW
Duplex Mode
0 = Normal operation
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared). With
auto-negotiation enabled, this bit reflects the duplex capability
50
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
