DM9016
3-port switch with Processor Interface
8. PHY Registers
MII Register Description
ADD Name
00H CONTR Reset
15
14
Loop
back
0
13
12
11
10
9
8
Full
7
6
5
4
3
2
1
0
Speed Auto-N Power Isolate Restart
select
1
Coll.
Test
0
Reserved
OL
Enable Down
1
Auto-N Duplex
0
0
0
0
1
000_0000
01H STATUS T4
TX FDX TX HDX 10 FDX 10 HDX
Reserved
Pream. Auto-N Remote Auto-N
Link
Status
0
Jabber
Detect
0
Extd
Cap.
1
Cap.
0
Cap.
Cap.
Cap.
Cap.
Supr.
Compl.
Fault
Cap.
1
0
0
1
0
1
1
0
1
1
0
1
0000
1
0
0
0
0
0
1
0
02H PHYID1
03H PHYID2
0
1
0
0
0
1
1
0
0
1
Model No.
01011
TX FDX TX HDX 10 FDX 10 HDX
Adv
LP
Version No.
0000
04H Auto-Neg. Next FLP Rcv Remote
Advertise Page
05H Link Part. LP
Reserved
FC
Adv
LP
T4
Adv
LP
Advertised Protocol Selector Field
Ack
Fault
Adv
LP
Adv
Adv
LP
LP
Reserved
LP
LP
Link Partner Protocol Selector Field
Ability
Next
Ack
RF
FC
T4
TX FDX TX HDX 10 FDX 10 HDX
Page
06H Auto-Neg.
Reserved
TX
Pardet LP Next Next Pg New Pg LP AutoN
Expansio
n
10H Specifie BP
Fault
Pg Able
Able
Rcv
Cap.
BP
SCR
BP
ALIGN
BP_ADP Reserve
Reserve Reserve Force Reserve Reserve RPDCTR Reset
100LNK -EN St. Mch
Pream.
Supr.
Sleep
mode
Remote
LoopOut
d
4B5B
OK
dr
d
d
d
d
Config.
11H Specifie 100
100
10
10 HDX Reserve Reverse Reverse
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
d
FDX
HDX
FDX
d
d
d
Conf/Stat
12H
10T
Conf/Stat
Rsvd
LP
Enable
HBE
SQUE
JAB
Reserve
d
Reserved
Polarity
Reverse
Enable Enable Enable
13H PWDOR
Reserved
PD10DR PD100l PDchip PDcrm PDaeq PDdrv
V
PDecli PDeclo PD10
14H Specifie TSTSE TSTSE FORCE FORCE PREA TX10M NWAY Reserv MDIX_ AutoNe Mdix_fix Mdix_d MonSel MonSel Reserv PD_val
d config
1
2
_TXSD _FEF MBLEX _PWR _PWR
ed
CNTL g_dlpbk Value
own
1
0
ed
ue
16H RCVER
Receiver Error Counter
17H DIS_conn
ect
Reversed
Disconnect_counter
Reversed
1DH PSCR
Reversed
PREA AMPLIT TX_P
MBLE UDE
X
WR
1EH DATA
1FH ADDR
indirect data
indirect address
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where:
<Reset Value>:
1
0
X
Bit set to logic one
Bit set to logic zero
No default value
<Access Type>:
RO = Read only,
<Attribute (s)>:
RW = Read/Write
SC = Self clearing, P = Value permanently set
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
49
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
