DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
BUSCR
INTCR
MONIR1
MONIR2
SCCR
Processor Bus Control Register
INT Pin Control Register
Monitor Register 1
Monitor Register 2
System Clock Turn ON Control Register
Resume System Clock Control Register
38H
39H
40H
41H
50H
51H
01H
00H
XXH
XXH
00H
XXH
XXH
RSCCR
MRCMDX
Memory Data Pre-Fetch Read Command Without Address F0H
Increment Register
MRCMDX1
MRCMD
Memory Data Read Command With Address Increment
Register
Memory Data Read Command With Address Increment
Register
F1H
XXH
XXH
F2H
MRRL
MRRH
MWCMDX
Memory Data Read_ address Register Low Byte
Memory Data Read_ address Register High Byte
Memory Data Write Command Without Address Increment F6H
Register
F4H
F5H
00H
00H
XXH
MWCMD
Memory Data Write Command With Address Increment
Register
F8H
XXH
MWRL
MWRH
TXPLL
TXPLH
ISR
Memory Data Write_ address Register Low Byte
Memory Data Write _ address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Status Register
FAH
FBH
FCH
FDH
FEH
FFH
00H
00H
XXH
XXH
00H
00H
IMR
Interrupt Mask Register
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
<Reset Value>:
1
0
X
Bit set to logic one
Bit set to logic zero
No default value
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
P = power on reset default value
H = hardware reset default value
S = software reset default value
Preliminary
15
Version: DM9010BI--DS-P01
January 12, 2010
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
