DM8203
2-port switch with MII / RMII Interface
The link status bit is implemented with a latching function, so that
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
1
0
Jabber detect
0, RO
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM8203 reset. This bit works only in
10Mbps mode
Extended
capability
1,RO/P Extended Capability
1 = Extended register capable
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM8203. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
15-0
OUI_MSB
<0181h>
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H
Bit
Bit Name
Default
Description
15-10
OUI_LSB
<101110>, OUI Least Significant Bits
RO/P
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
9-4
3-0
VNDR_MDL
MDL_REV
<001011>, Vendor Model Number
RO/P
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
<0000>,
RO/P
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
34
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
