DM8203
2-port switch with MII / RMII Interface
6.12 Per Port Status Data Register (62H)
Bit
7:6
5
Name
RESERVED
LP_FCS
BIST
Default
P0,RO
P0,RO
P0,RO
Description
Reserved
Link Partner Flow Control Enable Status
4
BIST status
1: SRAM BIST fail
0: SRAM BIST pass
Reserved
3
2
RESERVED
SPEED2
0,RO
P0,RO
PHY Speed Status
0: 10Mbps, 1:100Mbps
PHY Duplex Status
0: half-duplex, 1:full-duplex
PHY Link Status
1
0
FDX2
LINK2
P0,RO
P0,RO
0: link fail, 1: link OK
6.13 Per Port Forward Control Register (65H)
Bit Name Default
LOOPBACK PH0,RW
Description
Loop-Back Mode
7
6
The transmitted packet will be forward to this port itself.
MONI_TX
MONI_RX
DIS_BMP
PH0,RW
PH0,RW
TX Packet Monitored
The transmitted packets are also forward to sniffer port.
RX Packet Monitored
5
4
The received packets are also forward to sniffer port.
PH0,RW Broad/Multicast Not Monitored
The received broadcast or multicast packets are not forward to sniffer
port.
3
2
Reserved
TX_DIS
PH0,RW
PH0,RW
Reserved
Packet Transmit Disabled
All packets can not be forward to this port.
1
0
RX_DIS
PH0,RW
PH0,RW
Packet receive Disabled
All received packets are discarded.
Address Learning Disabled
ADR_DIS
The Source Address (SA) field of packet is not learned to address table.
Preliminarydatasheet
DM8203-15-DS-P05
October 23, 2008
19
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
