DM8203
2-port switch with MII / RMII Interface
6.7 Switch Control Register (52H)
Bit Name Default
MEM_BIST PH0,RO
Description
Address Table Memory Test BIST Status
7
0: OK
1: Fail
6
5
RST_SW
RST_ANLG P0,RW
P0,RW
Reset Switch Core and auto clear after 10us
Reset Analog PHY Core and auto clear after 10us
4:3
SNF_PORT PE00,RW Sniffer Port Number
Define the port number to act as the sniffer port
00
Port 0
01
Port 1
10
11
Port 2
Reserved
2
CRC_DIS
AGE
PE0,RW
PE0,RW
CRC Checking Disable
When set, the received CRC error packet also accepts to receive memory.
Address Table Aging
00: no aging
1:0
01: 64 ± 32 sec
10: 128 ± 64 sec
11: 256 ±128 sec
6.8 VLAN Control Register (53H)
Bit
7
Name
TOS6
Default
Description
PE0,RW Full IP ToS Field for Priority Queue
1: check most significant 6-bit of TOS
0: check most significant 3-bit only of TOS
6
5
4
RESERVED
UNICAST
VIDFF
0,RO
Reserved
PE0,RW Unicast packet can across VLAN boundary
PE0,RW Replace VIDFF
If the received packet is a tagged VLAN with VID equal to “FFF”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace VID01
If the received packet is a tagged VLAN with VID equal to “001”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace VID0
3
2
VID1
VID0
If the received packet is a tagged VLAN with VID equal to “000”, its VLAN field is
replaced with VLAN tag defined in Reg. 6EH and 6FH.
PE0,RW Replace priority field in the tag with value define in Reg 6FH bit 7~5.
PE0,RW VLAN mode enable
1
0
PRI
VLAN
1: 802.1Q base VLAN mode enable
0: port-base VLAN only
6.9 Switch Status Register (54H)
Bit
7
Name
MEM_BIST
Default
Description
PH0,RO Address Table Memory Test BIST Status
0: OK
1: Fail
6:0
RESERVED
0,RO
Reserved
Preliminarydatasheet
DM8203-15-DS-P05
October 23, 2008
17
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
