DM8203
2-port switch with MII / RMII Interface
6.22 Per Port VLAN Tag High Byte Register (6FH)
Bit
7:5
4
Name
PRI
CFI
Default
Description
PE0,RW Tag [15:13]
PE0,RW Tag[12]
PE0,RW VID[11:8]
3:0
VID118
6.23 MIB counters Port Index Register (80H)
Bit
7
Name
READY
Default
P0,RO
Description
MIB counter data is ready
When this register is written with INDEX data, this bit is cleared and the MIB
counter reading is in progress. After end of read MIB counter, the MIB data is
loaded into register 81H~84H, and this bit is set to indicate that the MIB data is
ready.
6:5
4:0
reserved
INDEX
0,RO
Reserved
PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81h~84h.
Write the MIB counter index to this register before read them.
6.24 MIB counter Data Register (81H~84H)
Bit
Name
Default
X,RO
X,RO
X,RO
X,RO
Description
81H
82H
83H
84H
Counter0
Counter1
Counter2
Counter3
Counter’s data bit 7~0
Counter’s data bit 15~8
Counter’s data bit 23~16
Counter’s data bit 31~24
MIB counter: RX Byte Counter Registers (INDEX 00H)
MIB counter: RX Uni-cast Packet Counter Registers (INDEX 01H)
MIB counter: RX Multi-cast Packet Counter Registers (INDEX 02H)
MIB counter: RX Discard Packet Counter Registers (INDEX 03H)
MIB counter: RX Error Packet Counter Registers (INDEX 04H)
MIB counter: TX Byte Counter Registers (INDEX 05H)
MIB counter: TX Uni-cast Packet Counter Registers (INDEX 06H)
MIB counter: TX Multi-cast Packet Counter Registers (INDEX 07H)
MIB counter: TX Discard Packet Counter Registers (INDEX 08H)
MIB counter: TX Error Packet Counter Registers (INDEX 09H)
Preliminarydatasheet
DM8203-15-DS-P05
October 23, 2008
23
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
