DM8203
2-port switch with MII / RMII Interface
6.1 EEPROM & PHY Control Register (0BH)
Bit
7:6
5
Name
RESERVED
REEP
Default
0,RO
Description
Reserved
PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
PH0,RW Write EEPROM Enable
4
WEP
3
EPOS
PH0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
1
0
ERPRR
ERPRW
ERRE
PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
PH0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
6.2 EEPROM & PHY Address Register (0CH)
Bit
7:6
5:0
Name
PHY_ADR PH01,RW PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0.
EROA PH0,RW EEPROM Word Address or PHY Register Address
Default
Description
6.3 EPROM & PHY Data Register (0DH~0EH)
Bit
Name
Default
Description
7:0
EE_PHY_L
PH0,RW EEPROM or PHY Low Byte Data (0DH)
This data is made to write/read low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0
EE_PHY_H
PH0,RW EEPROM or PHY High Byte Data (0EH)
This data is made to write/read high byte of word address defined in Reg. CH to
EEPROM or PHY
6.4 Vendor ID Register (28H~29H)
Bit
7:0
7:0
Name
VIDH
VIDL
Default
PE,0AH,RO
PE,46H.RO
Description
Description
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
6.5 Product ID Register (2AH~2BH)
Bit
7:0
7:0
Name
PIDH
PIDL
Default
PE,82H,RO
PE,03H.RO
Product ID High Byte (2BH)
Product ID Low Byte (2AH)
6.6 Port 2 driving capability Register (3AH)
Bit
Name
Default
Description
7
Reserved
0,RO
Reserved
Port 2 TXD/TXE Driving/Sinking Capability
00: 2mA
6:5
P2_CURR
P01,RW 01: 4mA (default)
10: 6mA
11: 8mA
4:0
RESERVED P01,RW reserved
16
Preliminary datasheet
DM8203-15-DS-P05
October 23, 2008
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
