DS2506
a program pulse is applied by the bus master, incorrect programming could occur within the DS2506.
Also note that the DS2506 will always increment its internal address counter after the receipt of the eight
read time slots used to confirm the programming of the selected EPROM byte. The decision to continue
is again made entirely by the bus master. Therefore if the EPROM data byte does not match the supplied
data byte but the master continues with the write command, incorrect programming could occur within
the DS2506. The write command sequence can be ended at any point by issuing a Reset Pulse.
WRITE MEMORY [0FH]/SPEED WRITE MEMORY [F3H]
The Write Memory command is used to program the 65536-bit EPROM data field. The details of the
functional flow chart are described in the section “WRITING EPROM MEMORY.”
The data memory address range is 0000H to 1FFFH. If the bus master sends a starting address higher than
this, the three most significant address bits are set to zeros by the internal circuitry of the chip. This will
result in a mismatch between the CRC calculated by the DS2506 and the CRC calculated by the bus
master, indicating an error condition.
To save time when writing more than one consecutive byte of the DS2506’s data memory it is possible to
omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the
EPROM memory. At regular speed this saves 16 time slots or 976 µs for every byte to be programmed.
This speed-programming mode is accessed with the command code F3H instead of 0FH. It follows
basically the same flow chart as the Write Memory command, but skips sending the CRC immediately
preceding the program pulse. This command should only be used if the electrical contact between bus
master and the DS2506 is firm since a poor contact may result in corrupted data inside the EPROM
memory.
WRITE STATUS [55H]/SPEED WRITE STATUS [F5H]
The Write Status command is used to program the 2816-bit EPROM Status Memory field. The details of
the functional flow chart are described in the section “WRITING EPROM MEMORY.”
The Status Memory address range is 0000H to 01FFH. Attempts to write to the not implemented status
memory locations will be ignored. If the bus master sends a starting address higher than 1FFFH, the three
most significant address bits are set to zeros by the internal circuitry of the chip. This will result in a
mismatch between the CRC calculated by the DS2506 and the CRC calculated by the bus master,
indicating an error condition. To save time when writing more than one consecutive byte of the
DS2506’s status memory it is possible to omit reading the 16-bit CRC which allows verification of data
and address before the data is copied to the EPROM memory. At regular speed this saves 16 time slots or
976 µs for every byte to be programmed. This speed-programming mode is accessed with the command
code F5H instead of 55H. It follows basically the same flow chart as the Write Status command, but skips
sending the CRC immediately preceding the program pulse. This command should only be used if the
electrical contact between bus master and the DS2506 is firm since a poor contact may result in corrupted
data inside the EPROM status memory.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the
DS2506 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signalling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
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DALLAS [ DALLAS SEMICONDUCTOR ]
