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DS2406P+R 参数 Datasheet PDF下载

DS2406P+R图片预览
型号: DS2406P+R
PDF下载: 下载PDF文件 查看货源
内容描述: 双寻址开关与1K位,内存 [Dual Addressable Switch Plus 1kbit Memory]
分类和应用: 开关
文件页数/大小: 31 页 / 350 K
品牌: DALLAS [ DALLAS SEMICONDUCTOR ]
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DS2406  
1-WIRE SIGNALING  
The DS2406 requires strict protocols to ensure data integrity. The protocol consists of five types of  
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data,  
and Program Pulse. Except for the presence pulse the bus master initiates all these signals.  
The initialization sequence required to begin any communication with the DS2406 is shown in Figure 14.  
A reset pulse followed by a presence pulse indicates the DS2406 is ready to send or receive data. The bus  
master transmits (TX) a reset pulse (tRSTL, minimum 480µs). The bus master then releases the line and  
goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pull-up resistor. After  
detecting the rising edge on the data pin, the DS2406 waits (tPDH, 15-60µs) and then transmits the  
presence pulse (tPDL, 60-240µs).  
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 14  
MASTER TX  
"RESET PULSE"  
MASTER RX "PRESENCE PULSE"  
t
V
RSTH  
PULLUP  
V
PULLUP MIN  
V
IH MIN  
V
IL MAX  
0V  
t
R
t
t
t
PDL  
RSTL  
PDH  
t
*
480 µs  
480 µs  
t
t
<
<
RSTL  
RESISTOR  
MASTER  
< 60 µs  
(includes recovery time)  
RSTH  
15 µs  
PDH  
DS2406  
60  
t
< 240 µs  
PDL  
* In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should  
always be less than 960µs. In a parasitically powered environment tRSTL should be limited to  
maximum 5ms. Otherwise the DS2406 may perform a power-on reset.  
READ/WRITE TIME SLOTS  
The definitions of write and read time slots are illustrated in Figure 15. The master initiates all time slots  
by driving the data line low. The falling edge of the data line synchronizes the DS2406 to the master by  
triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS2406  
will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit  
determines how long the DS2406 will hold the data line low. If the data bit is a “1”, the DS2406 will not  
hold the data line low at all.  
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