DS2176
SIGNALING SUPERVISION MODES Table 2
SM0
SM1
FMS
SELECTED MODE
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
193S framing, no integration, 1 multiframe freeze.
193E framing, no integration, 1 multiframe freeze.
193S framing, 2 multiframes integration and freeze.
193E framing, 2 multiframes integration and freeze.
193S framing, 5 multiframes integration, 2 multiframes freeze.
193E framing, 3 multiframes integration, 2 multiframes freeze.
1
01
11
193S framing, no integration, 1 multiframe freeze, replace robbed bit
signaling bits at SSER with ones.
193E framing, no integration, 1 multiframe freeze, replace robbed bit
signaling bits at SSER with ones.
1
1
1
0
1
1
NOTE:
1. During slip or alarm conditions, integration is limited to two multiframes to minimize signaling delay.
SLIP AND SIGNALING SUPERVISION LOGIC TIMING Figure 7
NOTES:
1. Integration feature disabled (SM0=SM1=0) in timing set shown.
2. Depending on present buffer depth, forcing ALN low may or may not cause a slip condition.
8 of 15
DALLAS [ DALLAS SEMICONDUCTOR ]
