DS2154
CCR3: COMMON CONTROL REGISTER 3 Address=1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
ESR
RSRE
THSE
TBCS
RCLA
SYMBOL
POSITION NAME AND DESCRIPTION
TESE
CCR3.7
CCR3.6
Transmit Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
TCBFS
Transmit Channel Blocking Registers (TCBR) Function
Select.
0=TCBRs define the operation of the TCHBLK output pin
1=TCBRs define which signaling bits are to be inserted
TIRFS
ESR
CCR3.5
CCR3.4
CCR3.3
Transmit Idle Registers (TIR) Function Select. See Section 8
for details.
0=TIRs define in which channels to insert idle code
1=TIRs define in which channels to insert data from RSER (i.e.,
Per=Channel Loopback function)
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. ESR is level triggered.
Should be toggled after RSYSCLK and TSYSCLK have been
applied and are stable. Must be set and cleared again for a
subsequent reset. Do not leave this bit set high.
RSRE
Receive Side Signaling Re-Insertion Enable. See Section 7-2
for details.
0=do not reinsert signaling bits into the data stream presented at
the RSER pin
1=reinsert the signaling bits into data stream presented at the
RSER pin
THSE
CCR3.2
Transmit Side Hardware Signaling Insertion Enable. See
Section 7-2 for details.
0=do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin
1=insert signaling from the TSIG pin into the data stream
presented at the TSER pin
TBCS
RCLA
CCR3.1
CCR3.0
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
Receive Carrier Loss (RCL) Alternate Criteria.
0=RCL declared upon 255 consecutive 0s (125 us)
1=RCL declared upon 2048 consecutive 0s (1 ms)
29 of 87
DALLAS [ DALLAS SEMICONDUCTOR ]
