DS2154
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB)
(LSB)
TESF
TESE
JALT
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
POSITION NAME AND DESCRIPTION
TESF
TESE
JALT
RIR.7
RIR.6
RIR.5
Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.
Transmit Side Elastic Store Empty. Set when the transmit side
elastic store buffer empties and a frame is repeated.
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
RESF
RESE
RIR.4
RIR.3
RIR.2
RIR.1
RIR.0
Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRCRC
FASRC
CASRC
CRC Resync Criteria Met. Set when 915/1000 code words are
received in error.
FAS Resync Criteria Met. Set when 3 consecutive FAS words
are received in error.
CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
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DALLAS [ DALLAS SEMICONDUCTOR ]
