DS2154
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2154,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event or an alarm occurs and a bit is set to a 1 in any of the
registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will
not be set again until the event has occurred again (or in the case of the RSA1, RSA0, RDMA, RUA1,
RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still present).
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2154 which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with the latest information. When a 0 is written to a bit
position, the read register will not be updated and the previous value will be held. A write to the status
and information registers will be immediately followed by a read of the same register. The read result
should be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS2154 with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT output pin.
Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt
pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively.
The interrupts caused by RUA1, RRA, RCL, and RLOS act differently than the interrupts caused by
RSA1, RDMA, RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP. The four
interrupts will force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or
inactive according to the set/ clear criteria in Table 4-1). The INT pin will be allowed to return high (if no
other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur If the
alarm is still present, the register bit will remain set.
The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
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DALLAS [ DALLAS SEMICONDUCTOR ]
