CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-25. 5V AC External Clock Specifications
Symbol
Description
Min
0.093
Typ
Max
24.6
Units
MHz
Notes
FOSCEXT
Frequency
–
–
–
–
High Period
Low Period
20.6
20.6
150
–
–
–
5300
ns
ns
µs
–
–
Power Up IMO to Switch
Table 3-26. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Frequency with CPU Clock divide by 1a
FOSCEXT
0.093
0.186
–
–
12.3
24.6
MHz
MHz
Frequency with CPU Clock divide by 2 or greaterb
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
FOSCEXT
–
–
–
41.7
41.7
150
–
–
–
5300
ns
ns
µs
–
–
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-27. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
ns
Notes
TRSCLK
Rise Time of SCLK
Fall Time of SCLK
1
–
20
20
–
TFSCLK
TSSCLK
THSCLK
FSCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB Flash Erase Time (Block)
–
10
10
–
–
TWRITE
TDSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
50
Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK
–
–
ns
3.0 ≤ Vdd ≤ 3.6
August 3, 2004
Document No. 38-12012 Rev. *I
34
CYPRESS [ CYPRESS ]
