CY8C24x23A Final Data Sheet
1. Pin Information
1.1.4
32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Type
CY8C24423A 32-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
IO
IO
P2[7]
P2[5]
P2[3]
P2[1]
Vss
IO
IO
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
Power
Power
P2[7]
P2[5]
1
2
3
4
5
6
7
8
P0[2], AI
P0[0], AI
24
23
22
21
20
19
18
SMP
Switch Mode Pump (SMP) connection to
external components required.
AI, P2[3]
AI, P2[1]
P2[6], External VRef
P2[4], External AGND
P2[2], AI
7
IO
IO
P1[7]
P1[5]
NC
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
No connection. Do not use.
MLF
(Top View)
Vss
SMP
8
P2[0], AI
9
I2C SCL, P1[7]
I2C SDA, P1[5]
XRES
10
11
12
13
IO
IO
P1[3]
P1[1]
Vss
17 P1[6]
Crystal Input (XTALin), I2C Serial Clock (SCL)
Ground connection.
Power
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA)
14
15
16
17
18
IO
IO
P1[2]
P1[4]
NC
Optional External Clock Input (EXTCLK)
No connection. Do not use.
IO
P1[6]
XRES
Input
Active high external reset with internal pull
down.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IO
IO
IO
IO
IO
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
NC
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VRef)
Analog column mux input.
I
I
Analog column mux input.
No connection. Do not use.
IO
IO
I
I
P0[4]
P0[6]
Vdd
Analog column mux input.
Analog column mux input.
Power
Supply voltage.
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
Analog column mux input.
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
September 8, 2004
Document No. 38-12028 Rev. *B
11
CYPRESS [ CYPRESS ]
