CY8C24x23A Final Data Sheet
1. Pin Information
1.1.3
28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Type
CY8C24423A 28-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
IO
IO
IO
IO
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
Analog column mux input.
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IO
IO
I
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
P0[6], AI
P0[4], AI
P0[2], AI
P2[7]
P0[0], AI
P2[5]
P2[6], External VRef
P2[4], External AGND
P2[2], AI
PDIP
SSOP
SOIC
AI, P2[3]
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
AI, P2[1]
SMP
P2[0], AI
Power
Power
Input
Switch Mode Pump (SMP) connection to
external components required.
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
XRES
P1[6]
10
11
12
13
14
15
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
P1[4], EXTCLK
P1[2]
I2C SCL, XTALin, P1[1]
Vss
P1[0], XTALout, I2C SDA
Crystal Input (XTALin), I2C Serial Clock (SCL)
Ground connection.
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA)
16
17
18
19
IO
IO
IO
P1[2]
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK)
Active high external reset with internal pull
down.
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND)
External Voltage Reference (VRef)
Analog column mux input.
I
I
I
I
Analog column mux input.
Analog column mux input.
Analog column mux input.
Power
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
September 8, 2004
Document No. 38-12028 Rev. *B
10
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