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CY8C24223-SPPVC 参数 Datasheet PDF下载

CY8C24223-SPPVC图片预览
型号: CY8C24223-SPPVC
PDF下载: 下载PDF文件 查看货源
内容描述: PSoC混合信号阵列 [PSoC Mixed Signal Array]
分类和应用:
文件页数/大小: 41 页 / 618 K
品牌: CYPRESS [ CYPRESS ]
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CY8C24x23 Final Data Sheet  
3. Electrical Specifications  
3.4.4  
AC Digital Block Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only or unless otherwise specified.  
Table 3-20. AC Digital Block Specifications  
Function  
Timer  
Description  
Min  
Typ  
Max  
Units  
ns  
Notes  
a
Capture Pulse Width  
50  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
49.2  
24.6  
MHz  
MHz  
ns  
4.75V < Vdd < 5.25V.  
a
Counter  
50  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
49.2  
24.6  
MHz  
MHz  
4.75V < Vdd < 5.25V.  
Dead Band Kill Pulse Width:  
Asynchronous Restart Mode  
20  
50  
ns  
ns  
a
a
Synchronous Restart Mode  
Disable Mode  
ns  
50  
Maximum Frequency  
49.2  
49.2  
MHz  
MHz  
4.75V < Vdd < 5.25V.  
4.75V < Vdd < 5.25V.  
CRCPRS  
Maximum Input Clock Frequency  
(PRS Mode)  
CRCPRS  
Maximum Input Clock Frequency  
24.6  
MHz  
(CRC Mode)  
SPIM  
SPIS  
Maximum Input Clock Frequency  
8.2  
4.1  
MHz  
ns  
Maximum Input Clock Frequency  
a
Width of SS_ Negated Between Transmissions  
ns  
50  
Transmitter Maximum Input Clock Frequency  
Receiver Maximum Input Clock Frequency  
16.4  
49.2  
MHz  
MHz  
16  
4.75V < Vdd < 5.25V.  
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).  
June 4, 2004  
Document No. 38-12011 Rev. *F  
31  
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