CY8C24x23 Final Data Sheet
3. Electrical Specifications
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
A
are for design guidance only or unless otherwise specified.
Table 3-23. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
24.24
Units
MHz
Notes
F
Frequency
0
–
OSCEXT
–
–
–
High Period
Low Period
20.6
20.6
150
–
–
–
–
–
–
ns
ns
µs
Power Up IMO to Switch
Table 3-24. 3.3V AC External Clock Specifications
Symbol
OSCEXT
OSCEXT
Description
Min
Typ
Max
Units
Notes
a
F
F
0
0
–
–
12.12
24.24
MHz
MHz
Frequency with CPU Clock divide by 1
b
Frequency with CPU Clock divide by 2 or greater
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
–
–
–
41.7
41.7
150
–
–
–
–
–
–
ns
ns
µs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
A
A
are for design guidance only or unless otherwise specified.
Table 3-25. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
ns
Notes
T
Rise Time of SCLK
Fall Time of SCLK
1
–
20
20
–
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
T
T
T
F
T
T
T
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
15
30
–
–
ERASEB
WRITE
DSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
June 4, 2004
Document No. 38-12011 Rev. *F
33
CYPRESS [ CYPRESS ]
