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CY8C21234-24SXI 参数 Datasheet PDF下载

CY8C21234-24SXI图片预览
型号: CY8C21234-24SXI
PDF下载: 下载PDF文件 查看货源
内容描述: 的PSoC ™混合信号阵列 [PSoC㈢ Mixed-Signal Array]
分类和应用:
文件页数/大小: 42 页 / 564 K
品牌: CYPRESS [ CYPRESS ]
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CY8C21x34 Final Data Sheet  
3. Electrical Specifications  
3.4  
AC Electrical Characteristics  
3.4.1  
AC Chip-Level Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C TA 85°C, 3.0V to 3.6V and -40°C TA 85°C, or 2.4V to 3.0V and -40°C TA 85°C, respectively. Typical parameters  
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.  
Table 3-15. 5V and 3.3V AC Chip-Level Specifications  
Symbol  
Description  
Min  
23.4  
Typ  
Max  
Units  
MHz  
Notes  
a,b,c  
F
F
Internal Main Oscillator Frequency for 24 MHz  
24  
6
Trimmed for 5V or 3.3V operation using  
factory trim values. See Figure 3-1b on  
page 17. SLIMO mode = 0.  
24.6  
IMO24  
a,b,c  
Internal Main Oscillator Frequency for 6 MHz  
5.75  
MHz  
Trimmed for 5V or 3.3V operation using  
factory trim values. See Figure 3-1b on  
page 17. SLIMO mode = 1.  
6.35  
IMO6  
a,b  
F
F
F
CPU Frequency (5V Nominal)  
CPU Frequency (3.3V Nominal)  
0.93  
0.93  
0
24  
12  
48  
MHz  
MHz  
MHz  
24 MHz only for SLIMO mode = 0.  
24.6  
12.3  
49.2  
CPU1  
CPU2  
BLK5  
b,c  
0
a,b,d  
Refer to the AC Digital Block Specifica-  
tions below.  
Digital PSoC Block Frequency (5V Nominal)  
b,d  
F
F
Digital PSoC Block Frequency (3.3V Nominal)  
Internal Low Speed Oscillator Frequency  
32 kHz RMS Period Jitter  
0
24  
32  
MHz  
kHz  
ns  
24.6  
64  
200  
BLK33  
32K1  
15  
Jitter32k  
Jitter32k  
100  
1400  
32 kHz Peak-to-Peak Period Jitter  
External Reset Pulse Width  
T
10  
40  
µs  
XRST  
DC24M  
24 MHz Duty Cycle  
50  
60  
%
Step24M  
Fout48M  
Jitter24M1  
24 MHz Trim Step Size  
50  
kHz  
MHz  
ps  
a,c  
48 MHz Output Frequency  
46.8  
48.0  
600  
Trimmed. Utilizing factory trim values.  
49.2  
24 MHz Peak-to-Peak Period Jitter (IMO)  
Maximum frequency of signal on row input or row output.  
Supply Ramp Time  
F
T
12.3  
MHz  
µs  
MAX  
0
RAMP  
a. 4.75V < Vdd < 5.25V.  
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.  
d. See the individual user module data sheets for information on maximum frequencies for user modules.  
Table 3-16. 2.7V AC Chip-Level Specifications  
Symbol  
Description  
Min  
11.5  
Typ  
Max  
Units  
MHz  
Notes  
0
a,b,c  
F
F
Internal Main Oscillator Frequency for 12 MHz  
Trimmed for 2.7V operation using factory  
trim values. See Figure 3-1b on page 17.  
SLIMO mode = 1.  
12  
6
12.7  
IMO12  
a,b,c  
Internal Main Oscillator Frequency for 6 MHz  
5.75  
MHz  
Trimmed for 2.7V operation using factory  
trim values. See Figure 3-1b on page 17.  
SLIMO mode = 1.  
6.35  
IMO6  
a,b  
F
F
CPU Frequency (2.7V Nominal)  
0.093  
0
3
MHz  
MHz  
24 MHz only for SLIMO mode = 0.  
3.15  
12.5  
CPU1  
a,b,c  
Digital PSoC Block Frequency (2.7V Nominal)  
12  
Refer to the AC Digital Block Specifica-  
tions below.  
BLK27  
F
Internal Low Speed Oscillator Frequency  
32 kHz RMS Period Jitter  
8
32  
96  
200  
kHz  
ns  
32K1  
Jitter32k  
Jitter32k  
150  
1400  
32 kHz Peak-to-Peak Period Jitter  
External Reset Pulse Width  
T
10  
µs  
XRST  
F
T
Maximum frequency of signal on row input or row output.  
Supply Ramp Time  
12.3  
MHz  
µs  
MAX  
0
RAMP  
a. 2.4V < Vdd < 3.0V.  
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.  
January 12, 2007  
Document No. 38-12025 Rev. *K  
24  
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