CY7C63722C
CY7C63723C
CY7C63743C
event, and subtracting the two values. The four capture timers
save a programmable 8 bit range of the free-running timer when
a GPIO edge occurs on the two capture pins (P0.0, P0.1).
The CY7C637xxC includes an integrated USB serial interface
engine (SIE) that supports the integrated peripherals. The
hardware supports one USB device address with three
endpoints. The SIE allows the USB host to communicate with the
function integrated into the microcontroller. A 3.3V regulated
output pin provides a pull-up source for the external USB resistor
on the D– pin.
The USB D+ and D– USB pins can alternately be used as PS/2
SCLK and SDATA signals, so that products can be designed to
respond to either USB or PS/2 modes of operation. PS/2
operation is supported with internal pull-up resistors on SCLK
and SDATA, the ability to disable the regulator output pin, and an
interrupt to signal the start of PS/2 activity. No external compo-
nents are necessary for dual USB and PS/2 systems, and no
GPIO pins need to be dedicated to switching between modes.
Slow edge rates operate in both modes to reduce EMI.
Pin Configurations
Top View
CY7C63723C
18-pin SOIC/PDIP
P0.0
P0.1
P0.2
P0.3
P1.0
VSS
VPP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P0.4
P0.5
P0.6
P0.7
P1.1
D+/SCLK
D–/SDATA
VCC
XTALOUT
CY7C63743C
24-pin SOIC/PDIP/QSOP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VPP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
D+/SCLK
D–/SDATA
VCC
XTALOUT
CY7C63722C-XC
DIE
3
2
1
25
24
23
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
4
5
6
7
8
9
22
21
20
19
18
P0.2
P0.1
P0.0
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
VSS 10
VPP 11
VREG 12
XTALIN/P2.1
XTALOUT
VCC
D-/SDATA
13
14
15
16
17 D+/SCLK
Pin Definitions
Name
D–/SDATA,
D+/SCLK
P0[7:0]
I/O
I/O
I/O
CY7C63723C CY7C63743C CY7C63722C
18-Pin
12
13
1, 2, 3, 4,
15, 16, 17, 18
24-Pin
15
16
25-Pad
16
17
Description
USB differential data lines (D– and D+), or PS/2 clock
and data signals (SDATA and SCLK)
1, 2, 3, 4,
1, 2, 3, 4,
GPIO Port 0 capable of sinking up to 50 mA/pin, or
21, 22, 23, 24 22, 23, 24, 25 sinking controlled low or high programmable current.
Can also source 2 mA current, provide a resistive
pull-up, or serve as a high-impedance input. P0.0 and
P0.1 provide inputs to Capture Timers A and B, respec-
tively.
5, 6, 7, 8,
5, 6, 7, 8,
IO Port 1 capable of sinking up to 50 mA/pin, or sinking
17, 18, 19, 20 18, 19, 20, 21 controlled low or high programmable current. Can also
source 2 mA current, provide a resistive pull-up, or
serve as a high-impedance input.
12
13
10
14
11
9
13
14
11
15
12
9, 10
6-MHz ceramic resonator or external clock input, or
P2.1 input
6-MHz ceramic resonator return pin or internal oscillator
output
Programming voltage supply, ground for normal
operation
Voltage supply
Voltage supply for 1.3-k USB pull-up resistor (3.3V
nominal). Also serves as P2.0 input.
Ground
P1[7:0]
I/O
5, 14
XTALIN/P2.1
XTALOUT
V
PP
V
CC
VREG/P2.0
V
SS
IN
OUT
9
10
7
11
8
6
Document #: 38-08022 Rev. *E
Page 3 of 53
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