CY7C63722C
CY7C63723C
CY7C63743C
Logic Block Diagram
XTALIN/P2.1
XTALOUT
Internal
Oscillator
Xtal
Oscillator
8-bit
RISC
Core
Wake-Up
Timer
RAM
256 Byte
12-bit
Timer
Capture
Timers
SPI
EPROM
8K Byte
Brown-out
Reset
Watch
Dog
Timer
Low
Voltage
Reset
Interrupt
Controller
USB
Engine
USB &
PS/2
Xcvr
Port 1
GPIO
Port 0
GPIO
3.3V
Regulator
VREG/P2.0
D+,D–
P1.0–P1.7
P0.0–P0.7
Functional Overview
enCoRe USB—The New USB Standard
Cypress has reinvented its leadership position in the low-speed
USB
market
with
a
new
family
of
innovative
microcontrollers. Introducing...enCoRe USB—“enhanced
Component Reduction.” Cypress has leveraged its design
expertise in USB solutions to create a new family of low-speed
USB microcontrollers that enables peripheral developers to
design new products with a minimum number of components. At
the heart of the enCoRe USB technology is the breakthrough
design of a crystalless oscillator. By integrating the oscillator into
our chip, an external crystal or resonator is no longer needed.
We have also integrated other external components commonly
found in low-speed USB applications such as pull-up resistors,
wake-up circuitry, and a 3.3V regulator. All of this adds up to a
lower system cost.
The CY7C637xxC is an 8-bit RISC one-time-programmable
(OTP) microcontroller. The instruction set has been optimized
specifically for USB and PS/2 operations, although the microcon-
trollers can be used for a variety of other embedded applications.
The CY7C637xxC features up to 16 GPIO pins to support USB,
PS/2 and other applications. The I/O pins are grouped into two
ports (Port 0 to 1) where each pin can be individually configured
as inputs with internal pull-ups, open drain outputs, or traditional
CMOS outputs with programmable drive strength of up to 50 mA
output drive. Additionally, each I/O pin can be used to generate
a GPIO interrupt to the microcontroller. Note the GPIO interrupts
all share the same “GPIO” interrupt vector.
The CY7C637xxC microcontrollers feature an internal oscillator.
With the presence of USB traffic, the internal oscillator can be set
to precisely tune to USB timing requirements (6 MHz ±1.5%).
Document #: 38-08022 Rev. *E
Optionally, an external 6-MHz ceramic resonator can be used to
provide a higher precision reference for USB operation. This
clock generator reduces the clock-related noise emissions
(EMI). The clock generator provides the 6- and 12-MHz clocks
that remain internal to the microcontroller.
The CY7C637xxC has 8 Kbytes of EPROM and 256 bytes of
data RAM for stack space, user variables, and USB FIFOs.
These parts include low-voltage reset logic, a Watchdog timer, a
vectored interrupt controller, a 12-bit free-running timer, and
capture timers. The low-voltage reset (LVR) logic detects when
power is applied to the device, resets the logic to a known state,
and begins executing instructions at EPROM address 0x0000.
LVR will also reset the part when V
CC
drops below the operating
voltage range. The Watchdog timer can be used to ensure the
firmware never gets stalled for more than approximately 8 ms.
The microcontroller supports 10 maskable interrupts in the
vectored interrupt controller. Interrupt sources include the USB
Bus-Reset, the 128-s and 1.024-ms outputs from the
free-running timer, three USB endpoints, two capture timers, an
internal wake-up timer and the GPIO ports. The timers bits cause
periodic interrupts when enabled. The USB endpoints interrupt
after USB transactions complete on the bus. The capture timers
interrupt whenever a new timer value is saved due to a selected
GPIO edge event. The GPIO ports have a level of masking to
select which GPIO inputs can cause a GPIO interrupt. For
additional flexibility, the input transition polarity that causes an
interrupt is programmable for each GPIO pin. The interrupt
polarity can be either rising or falling edge.
The free-running 12-bit timer clocked at 1 MHz provides two
interrupt sources as noted above (128
s
and 1.024 ms). The
timer can be used to measure the duration of an event under
firmware control by reading the timer at the start and end of an
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