CY7C63722C
CY7C63723C
CY7C63743C
Table 1. I/O Register Summary
(continued)
Register Name
USB Device Address
EP0 Counter Register
EP0 Mode Register
EP1 Counter Register
EP1 Mode Register
EP2 Counter Register
EP2 Mode Register
USB Status & Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer (LSB)
Timer (MSB)
WDR Clear
Capture Timer A Rising
Capture Timer A Falling
Capture Timer B Rising
Capture Timer B Falling
Capture TImer Configuration
Capture Timer Status
SPI Data
SPI Control
Clock Configuration
Processor Status & Control
I/O Address
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x1F
0x20
0x21
0x24
0x25
0x26
0x40
0x41
0x42
0x43
0x44
0x45
0x60
0x61
0xF8
0xFF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
R
R
R
R
R/W
R
R/W
R/W
R/W
R/W
Function
USB Device Address register
USB Endpoint 0 counter register
USB Endpoint 0 configuration register
USB Endpoint 1 counter register
USB Endpoint 1 configuration register
USB Endpoint 2 counter register
USB Endpoint 2 configuration register
USB status and control register
Global interrupt enable register
USB endpoint interrupt enables
Lower 8 bits of free-running timer (1 MHz)
Upper 4 bits of free-running timer
Watchdog Reset clear
Rising edge Capture Timer A data register
Falling edge Capture Timer A data register
Rising edge Capture Timer B data register
Falling edge Capture Timer B data register
Capture Timer configuration register
Capture Timer status register
SPI read and write data register
SPI status and control register
Internal / External Clock configuration register
Processor status and control
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Fig
Document #: 38-08022 Rev. *E
Page 9 of 53
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