CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
10.10 Slave FIFO Asynchronous Write
t
WRpwh
SLWR
SLWR/SLCS#
t
WRpwl
t
t
FDH
SFD
DATA
t
XFD
FLAGS
Figure 10-10. Slave FIFO Asynchronous Write Timing Diagram[20]
Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [23]
Parameter
tWRpwl
tWRpwh
tSFD
Description
Min.
50
Max.
Unit
ns
SLWR Pulse LOW
SLWR Pulse HIGH
70
ns
SLWR to FIFO DATA Set-up Time
FIFO DATA to SLWR Hold Time
10
ns
tFDH
10
ns
tXFD
SLWR to FLAGS Output Propagation Delay
70
ns
10.11 Slave FIFO Synchronous Packet End Strobe
IFCLK
t
PEH
PKTEND
FLAGS
t
SPE
t
XFLG
Figure 10-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram[20]
Table 10-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min.
20.83
14.6
0
Max.
Unit
ns
IFCLK Period
tSPE
tPEH
tXFLG
PKTEND to Clock Set-up Time
ns
Clock to PKTEND Hold Time
ns
Clock to FLAGS Output Propagation Delay
9.5
ns
Table 10-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min.
20.83
8.6
Max.
Unit
ns
IFCLK Period
200
tSPE
tPEH
tXFLG
PKTEND to Clock Set-up Time
ns
Clock to PKTEND Hold Time
2.5
ns
Clock to FLAGS Output Propagation Delay
13.5
ns
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is the set-up
time tSPE and the hold time tPEH must be met.
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition
that needs attention while using the PKTEND to commit a one
byte/word packet. There is an additional timing requirement
that need to be met when the FIFO is configured to operate in
Document #: 38-08032 Rev. *K
Page 46 of 60
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