CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
10.15 Slave FIFO Synchronous Address
IFCLK
SLCS/FIFOADR [1:0]
t
t
FAH
SFA
Figure 10-16. Slave FIFO Synchronous Address Timing Diagram[20]
Table 10-17. Slave FIFO Synchronous Address Parameters [21]
Parameter Description
tIFCLK Interface Clock Period
tSFA
tFAH
Min.
20.83
25
Max.
Unit
ns
200
FIFOADR[1:0] to Clock Set-up Time
Clock to FIFOADR[1:0] Hold Time
ns
10
ns
10.16 Slave FIFO Asynchronous Address
SLCS/FIFOADR [1:0]
t
FAH
t
SFA
SLRD/SLWR/PKTEND
Figure 10-17. Slave FIFO Asynchronous Address Timing Diagram[20]
Slave FIFO Asynchronous Address Parameters[23]
Parameter
Description
Min.
10
Max.
Unit
ns
tSFA
tFAH
FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
Document #: 38-08032 Rev. *K
Page 49 of 60
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