CY7C64013
CY7C64113
Table 4-2. I/O Register Summary (continued)
I/O Address Read/Write
Register Name
GPIO Configuration
HAPI and I2C Configuration
USB Device Address A
EP A0 Counter Register
EP A0 Mode Register
EP A1 Counter Register
EP A1 Mode Register
EP A2 Counter Register
EP A2 Mode Register
USB Status & Control
Global Interrupt Enable
Endpoint Interrupt Enable
Interrupt Vector
Function
GPIO Port Configurations
HAPI Width and I2C Position Configuration
Page
19
0x08
0x09
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x1F
0x20
0x21
0x23
0x24
0x25
0x26
0x28
0x29
0x30
0x31
0x32
0x38-0x3F
0x40
0x41
0x42
0x43
0x44
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0xFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
22
USB Device Address A
32
USB Address A, Endpoint 0 Counter
USB Address A, Endpoint 0 Configuration
USB Address A, Endpoint 1 Counter
USB Address A, Endpoint 1 Configuration
USB Address A, Endpoint 2 Counter
USB Address A, Endpoint 2 Configuration
33
32
33
33
33
33
USB Upstream Port Traffic Status and Control
Global Interrupt Enable
USB Endpoint Interrupt Enables
Pending Interrupt Vector Read / Clear
Lower 8 Bits of Free-running Timer (1 MHz)
Upper 4 Bits of Free-running Timer
Watch Dog Timer Clear
I2C Status and Control
I2C Data
31
26
26
28
21
21
16
23
23
20
21
21
20
Timer (LSB)
R
Timer (MSB)
R
WDT Clear
W
I2C Control & Status
I2C Data
R/W
R/W
R/W
W
DAC Data
DAC Data
DAC Interrupt Enable
DAC Interrupt Polarity
DAC Isink
Interrupt Enable for each DAC Pin
Interrupt Polarity for each DAC Pin
Input Sink Current Control for each DAC Pin
Reserved
W
W
Reserved
EP A3 Counter Register
EP A3 Mode Register
EP A4 Counter Register
EP A4 Mode Register
Reserved
R/W
R/W
R/W
R/W
USB Address A, Endpoint 3 Counter
USB Address A, Endpoint 3 Configuration
USB Address A, Endpoint 4 Counter
USB Address A, Endpoint 4 Configuration
Reserved
33
32
33
33
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Processor Status & Control
R/W
Microprocessor Status and Control Register
25
Document #: 38-08001 Rev. **
Page 10 of 48
CYPRESS [ CYPRESS ]
