FOR
FOR
enCoRe™
USB CY7C63722/23
CY7C63743
The SPI Data Register below serves as a transmit and receive buffer.
Bit #
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
Data I/O
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
Figure 17-2. SPI Data Register (Address 0x60)
Bit [7:0]: Data I/O[7:0]
Writes to the SPI Data Register load the transmit buffer, while reads from this register read the receive buffer contents.
1 = Logic HIGH
0 = Logic LOW
17.1
Operation as an SPI Master
Only an SPI Master can initiate a byte/data transfer. This is done by the Master writing to the SPI Data Register. The Master shifts
out 8 bits of data (MSB first) along with the serial clock SCK for the Slave. The Master’s outgoing byte is replaced with an incoming
one from a Slave device. When the last bit is received, the shift register contents are transferred to the receive buffer and an
interrupt is generated. The receive data must be read from the SPI Data Register before the next byte of data is transferred to
the receive buffer, or the data will be lost.
When operating as a Master, an active LOW Slave Select (SS) must be generated to enable a Slave for a byte transfer. This
Slave Select is generated under firmware control, and is not part of the SPI internal hardware. Any available GPIO can be used
for the Master’s Slave Select output.
When the Master writes to the SPI Data Register, the data is loaded into the transmit buffer. If the shift register is not busy shifting
a previous byte, the TX buffer contents will be automatically transferred into the shift register and shifting will begin. If the shift
register is busy, the new byte will be loaded into the shift register only after the active byte has finished and is transferred to the
receive buffer. The new byte will then be shifted out. The Transmit Buffer Full (TBF) bit will be set HIGH until the transmit buffer’s
data-byte is transferred to the shift register. Writing to the transmit buffer while the TBF bit is HIGH will overwrite the old byte in
the transmit buffer.
The byte shifting and SCK generation are handled by the hardware (based on firmware selection of the clock source). Data is
shifted out on the MOSI pin (P0.5) and the serial clock is output on the SCK pin (P0.7). Data is received from the slave on the
MISO pin (P0.6). The output pins must be set to the desired drive strength, and the GPIO data register must be set to 1 to enable
a bypass mode for these pins. The MISO pin must be configured in the desired GPIO input mode. See Section 12.0 for GPIO
configuration details.
17.2
Master SCK Selection
The Master’s SCK is programmable to one of four clock settings, as shown in
The frequency is selected with the
Clock Select Bits of the SPI control register. The hardware provides 8 output clocks on the SCK pin (P0.7) for each byte transfer.
Clock phase and polarity are selected by the CPHA and CPOL control bits (see
and
The master SCK duty cycle is nominally 33% in the fastest (2 Mbps) mode, and 50% in all other modes.
17.3
Operation as an SPI Slave
In slave mode, the chip receives SCK from an external master on pin P0.7. Data from the master is shifted in on the MOSI pin
(P0.5), while data is being shifted out of the slave on the MISO pin (P0.6). In addition, the active LOW Slave Select must be
asserted to enable the slave for transmit. The Slave Select pin is P0.4. These pins must be configured in appropriate GPIO modes,
with the GPIO data register set to 1 to enable bypass mode selected for the MISO pin.
In Slave mode, writes to the SPI Data Register load the Transmit buffer. If the Slave Select is asserted (SS LOW) and the shift
register is not busy shifting a previous byte, the transmit buffer contents will be automatically transferred into the shift register. If
the shift register is busy, the new byte will be loaded into the shift register only after the active byte has finished and is transferred
to the receive buffer. The new byte is then ready to be shifted out (shifting waits for SCK from the Master). If the Slave Select is
not active when the transmit buffer is loaded, data is not transferred to the shift register until Slave Select is asserted. The Transmit
Buffer Full (TBF) bit will be set to ‘1’ until the transmit buffer’s data-byte is transferred to the shift register. Writing to the transmit
buffer while the TBF bit is HIGH will overwrite the old byte in the Transmit Buffer.
If the Slave Select is deasserted before a byte transfer is complete, the transfer is aborted and no interrupt is generated. Whenever
Slave Select is asserted, the transmit buffer is automatically reloaded into the shift register.
Clock phase and polarity must be selected to match the SPI master, using the CPHA and CPOL control bits (see
and
Document #: 38-08022 Rev. **
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