FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
has lasted for 128–256 µs, and the bit will be set even if the interrupt is not enabled. The bit is only cleared by firmware or
LVR/WDR.
1 = A USB reset occurred or PS/2 Activity is detected, depending on USB-PS/2 Interrupt Select bit.
0 = No event detected since last cleared by firmware or LVR/WDR.
Bit 4: LVR/BOR Reset
The Low-voltage or Brown-out Reset is set to ‘1’ during a power-on reset. Firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a LVR/BOR condition or a watchdog timeout. This bit is not affected by WDR.
Note that a LVR/BOR event may be followed by a watchdog reset before firmware begins executing, as explained at the end
of this section.
1 = A POR or LVR has occurred.
0 = No POR nor LVR since this bit last cleared.
Bit 3: Suspend
Writing a '1' to the Suspend bit will halt the processor and cause the microcontroller to enter the suspend mode that significantly
reduces power consumption. An interrupt or USB bus activity will cause the device to come out of suspend. After coming out
of suspend, the device will resume firmware execution at the instruction following the IOWR which put the part into suspend.
When writing the suspend bit with a resume condition present (such as non-idle USB activity), the suspend state will still be
entered, followed immediately by the wake-up process (with appropriate delays for the clock start-up). See Section 11.0 for
more details on suspend mode operation.
1 = Suspend the processor.
0 = Not in suspend mode. Cleared by the hardware when resuming from suspend.
Bit 2: Interrupt Enable Sense
This bit shows whether interrupts are enabled or disabled. Firmware has no direct control over this bit as writing a zero or one
to this bit position will have no effect on interrupts. This bit is further gated with the bit settings of the Global Interrupt Enable
Register (Figure 21-1) and USB Endpoint Interrupt Enable Register (Figure 21-2). Instructions DI, EI, and RETI manipulate
the state of this bit.
1 = Interrupts are enabled.
0 = Interrupts are masked off.
Bit 1: Reserved. Must be written as a 0.
Bit 0: Run
This bit is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the end
of the current instruction. The processor remains halted until a reset occurs (low-voltage, brown-out, or watchdog). This bit
should normally be written as a ‘1’.
During power-up, or during a low-voltage reset, the Processor Status and Control Register is set to 00010001, which indicates a
LVR/BOR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). Note that during the tSTART ms partial suspend at
start-up (explained in Section 10.1), a Watchdog Reset will also occur. When a WDR occurs during the power-up suspend interval,
firmware would read 01010001 from the Status and Control Register after power-up. Normally the LVR/BOR bit should be cleared
so that a subsequent WDR can be clearly identified. Note that if a USB bus reset (long SE0) is received before firmware examines
this register, the Bus Interrupt Event bit would also be set.
During a Watchdog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watchdog Reset (bit
4 set) has occurred and no interrupts are pending (bit 7 clear).
21.0
Interrupts
Interrupts can be generated by the GPIO lines, the internal free-running timer, the SPI block, the capture timers, on various USB
events, PS/2 activity, or by the wake-up timer. All interrupts are maskable by the Global Interrupt Enable Register and the USB
End Point Interrupt Enable Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position. During a
reset, the contents of the interrupt enable registers are cleared, along with the Global Interrupt enable bit of the CPU, effectively
disabling all interrupts.
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 21-3 for the logic block diagram of the interrupt
controller. When an interrupt is generated it is first registered as a pending interrupt. It will stay pending until it is serviced or a
reset occurs. A pending interrupt will only generate an interrupt request if it is enabled by the corresponding bit in the interrupt
enable registers. The highest priority interrupt request will be serviced following the completion of the currently executing
instruction.
Document #: 38-08022 Rev. **
Page 36 of 58
CYPRESS [ CYPRESS ]
