CY7C1470V25
CY7C1472V25
CY7C1474V25
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL
TM
Architecture
Features
■
■
Functional Description
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2
M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations
with
no
wait
states.
The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible
and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BW
a
–BW
h
for CY7C1474V25, BW
a
–BW
d
for CY7C1470V25
and BW
a
–BW
b
for CY7C1472V25) and a write enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
❐
Available speed grades are 250, 200 and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 2.5 V power supply
2.5 V/1.8 V I/O supply (V
DDQ
)
Fast clock-to-output times
❐
3.0 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1470V25, CY7C1472V25 available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and
non Pb-free 165-ball FBGA package. CY7C1474V25 available
in Pb-free and non Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG boundary scan compatible
Burst capability—linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram - CY7C1470V25 (2 M × 36)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
a
DQP
b
DQP
c
DQP
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document Number: 38-05290 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 28, 2011
CYPRESS [ CYPRESS SEMICONDUCTOR ]
