CY7C1360B
CY7C1362B
Switching Characteristics Over the Operating Range[16, 17]
225 MHz
200 MHz
166 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min.
1
Max
Min.
1
Max
Min.
1
Max
Unit
ms
VDD(Typical) to the First Access[18]
Clock Cycle Time
Clock HIGH
4.4
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Clock LOW
Output Times
tCO
tDOH
tCLZ
tCHZ
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[19, 20, 21]
2.8
3.0
3.5
ns
ns
ns
ns
ns
ns
ns
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
Clock to High-Z[19, 20, 21]
2.8
2.8
3.0
3.0
3.5
3.5
tOEV
OE LOW to Output Valid
LOW to Output Low-Z[19, 20, 21]
OE
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
tWES
0
0
0
OE HIGH to Output High-Z[19, 20, 21]
2.8
3.0
3.5
Address Set-up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
,
ADSC ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
Set-up before CLK Rise
GW, BWE, BWX
tDS
tCES
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Hold Times
tAH
tADH
tADVH
tWEH
tDH
Address Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
Hold after CLK Rise
ADSP ADSC
ADV Hold after CLK Rise
,
,
GW BWE BWX Hold after CLK Rise
Data Input Hold after CLK Rise
tCEH
Chip Enable Hold after CLK Rise
Shaded areas contain advance information.
Notes:
16. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
DD
POWER
19. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
21. This parameter is sampled and not 100% tested.
Document #: 38-05291 Rev. *C
Page 25 of 34
CYPRESS [ CYPRESS ]
