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CY7C1360B-166AC 参数 Datasheet PDF下载

CY7C1360B-166AC图片预览
型号: CY7C1360B-166AC
PDF下载: 下载PDF文件 查看货源
内容描述: 9兆位( 256K ×36 / 512K ×18 )流水线式SRAM [9-Mbit (256K x 36/512K x 18) Pipelined SRAM]
分类和应用: 静态存储器
文件页数/大小: 34 页 / 859 K
品牌: CYPRESS [ CYPRESS ]
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CY7C1360B  
CY7C1362B  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... >2001V  
(Above which the useful life may be impaired. For user guide-  
(per MIL-STD-883, Method 3015)  
lines, not tested.)  
Latch-up Current..................................................... >200 mA  
Storage Temperature .................................65°C to +150°C  
Ambient Temperature with  
Operating Range  
Power Applied.............................................55°C to +125°C  
Ambient  
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V  
Range  
Temperature  
VDD  
VDDQ  
DC Voltage Applied to Outputs  
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%  
in Three-State ..................................... –0.5V to VDDQ + 0.5V  
to VDD  
Industrial  
–40°C to +85°C  
DC Input Voltage....................................–0.5V to VDD + 0.5V  
Electrical Characteristics Over the Operating Range[13, 14]  
Parameter  
VDD  
VDDQ  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
3.6  
VDD  
Unit  
V
V
VDDQ = 3.3V  
VDDQ = 2.5V  
2.625  
VOH  
VOL  
VIH  
VIL  
IX  
Output HIGH Voltage  
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA  
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA  
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA  
V
V
V
V
V
V
V
V
µA  
2.0  
Output LOW Voltage  
0.4  
0.4  
VDD + 0.3V  
VDD + 0.3V  
0.8  
V
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA  
Input HIGH Voltage[13] VDDQ = 3.3V  
2.0  
1.7  
–0.3  
–0.3  
–5  
VDDQ = 2.5V  
Input LOW Voltage[13]  
VDDQ = 3.3V  
VDDQ = 2.5V  
GND VI VDDQ  
0.7  
5
Input Load Current  
except ZZ and MODE  
Input Current of MODE Input = VSS  
Input = VDD  
–30  
–5  
µA  
µA  
µA  
µA  
µA  
5
Input Current of ZZ  
Input = VSS  
Input = VDD  
30  
5
IOZ  
IDD  
Output Leakage Current GND VI VDDQ, Output Disabled  
–5  
VDD Operating Supply VDD = Max., IOUT = 0 mA,  
4.4-ns cycle, 225 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
All speeds  
250  
220  
180  
50  
mA  
mA  
mA  
mA  
Current  
f = fMAX = 1/tCYC  
ISB1  
ISB2  
ISB3  
ISB4  
Automatic CE  
VDD = Max, Device Deselected,  
Power-down  
VIN VIH or VIN VIL  
Current—TTL Inputs  
f = fMAX = 1/tCYC  
Automatic CE  
VDD = Max, Device Deselected,  
All speeds  
30  
50  
40  
mA  
mA  
mA  
Power-down  
V
IN 0.3V or VIN > VDDQ – 0.3V,  
Current—CMOS Inputs f = 0  
Automatic CE  
VDD = Max, Device Deselected, or All speeds  
Power-down  
V
IN 0.3V or VIN > VDDQ – 0.3V  
Current—CMOS Inputs f = fMAX = 1/tCYC  
Automatic CE  
VDD = Max, Device Deselected,  
All Speeds  
Power-down  
VIN VIH or VIN VIL, f = 0  
Current—TTL Inputs  
Shaded areas contain advance information.  
Notes:  
13. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t  
/2).  
IH  
DD  
CYC  
IL  
CYC  
14. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
DD  
Power-up  
DD  
IH  
DD  
DDQ  
Document #: 38-05291 Rev. *C  
Page 23 of 34  
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