CY7C1360B
CY7C1362B
Identification Register Definitions
CY7C1360B
CY7C1362B
(512KX18)
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
(256KX36)
001
Description
Describes the version number
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
001
01010
01010
000000
010110
Device Width (23:18)
000000
100110
00000110100
1
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
00000110100 Allows unique identification of SRAM vendor
1
Indicates the presence of an ID register
Scan Register Sizes
Bit Size(x36)
Register Name
Bit Size(x18)
Instruction
Bypass
3
1
3
1
ID
32
71
32
71
Boundary Scan Order
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05291 Rev. *C
Page 20 of 34
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