CY7C1360B
CY7C1362B
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1360B/CY7C1362B incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure .
TDI is internally pulled up and can be unconnected if the TAP
is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1360B/CY7C1362B contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
Selection
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05291 Rev. *C
Page 16 of 34
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