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CY7C1041CV33-10ZC 参数 Datasheet PDF下载

CY7C1041CV33-10ZC图片预览
型号: CY7C1041CV33-10ZC
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 256K ×16 )静态RAM [4-Mbit (256K x 16) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 599 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1041CV33
AC Switching Characteristics
[5]
Over the Operating Range (continued)
-10
Parameter
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Cycle
[9, 10]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to
Low-Z
[7]
WE LOW to High-Z
[7, 8]
Byte Enable to End of Write
7
10
7
7
0
0
7
5
0
3
5
8
12
8
8
0
0
8
6
0
3
6
10
15
10
10
0
0
10
7
0
3
7
10
20
10
10
0
0
10
8
0
3
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IISB
SB
IICC
CC
HIGH
IMPEDANCE
DATA OUT
Notes:
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
11. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05134 Rev. *H
Page 6 of 12