CY7C1041CV33
Thermal Resistance
[3]
Parameter
Description
Test Conditions
TSOP-II
42.96
10.75
FBGA
38.15
9.15
SOJ
25.99
18.8
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Thermal Resistance (Junction to Ambient) Test conditions follow standard
Thermal Resistance (Junction to Case) test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
AC Test Loads and Waveforms
[4]
10-ns Devices
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Z = 50Ω
12-, 15-, 20-ns Devices
3.3V
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
High-Z Characteristics
R 317Ω
(a)
ALL INPUT PULSES
(b)
3.3V
OUTPUT
5 pF
R2
351Ω
3.0V
90%
GND
10%
90%
10%
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
AC Switching Characteristics
[5]
Over the Operating Range
-10
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[7, 8]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
0
6
0
10
5
0
6
3
5
0
12
6
0
7
0
5
3
6
0
15
7
0
8
3
10
5
0
6
3
7
0
20
8
100
10
10
3
12
6
0
7
3
8
100
12
12
3
15
7
0
8
100
15
15
3
20
8
100
20
20
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
Notes:
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
Write.
Document #: 38-05134 Rev. *H
Page 5 of 12
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